Field
The present invention relates generally to a method and apparatus to allow a computer system to receive information while the CPU is in a sleeping state, and more particularly to a first peripheral device with multiple modes of operation to receive, buffer, and process data, including directly accessing a second peripheral device, while the computer""s CPU is in a sleeping or suspended state.
As mobile computing devices seek to extend time-of-operation between charges, power management has become increasingly important. One way in which power management is accomplished is by completely, or partially, shutting down computer components, such as the central processing unit (CPU), hard disk drive, display, and other input/output (I/O) devices: when the computer is not performing operations.
During some of these power management modes, also known as sleeping states, the computer""s CPU may cease communications with and control of its peripheral resources, including I/O components, and those resources may not be accessed by any other computer component. Such power management techniques are not unique to any one computer system architecture.
One hardware system specification, the Advanced Configuration and Power Interface (ACPI) Specification, by Intel, Microsoft, and Toshiba, Revision 1.0b, Feb. 2, 1999, provides a technique for enhancing power management in a personal computer (PC) system architecture. The ACPI specification describes the transfer of power management functions from the Basic Input/Output System (BIOS) to the operating system, thereby enabling demand-based peripheral and power management. Through the application of this specification, PC computers manage power usage of peripheral devices such as CD-ROMs, network cards, hard disk drives, audio codecs, and printers, as well as consumer electronics connected to a PC, such as video cassette recorders, television sets, telephones, and stereos.
As shown in the table below, the ACPI specification defines several low-power sleeping states, S1-S5, that reduce the power consumed by the CPU by limiting the operations it may perform. S0 is herein used as an indicator of xe2x80x98no sleeping statexe2x80x99. These various operating states are herein referred to as power management states. xe2x80x98Contextxe2x80x99, refers to variable data held by the CPU and other computer devices. It is usually volatile and can be lost when entering or leaving certain sleeping states.
Sleeping Description
States
S0 Normal operation, active state.
S1 The S1 sleeping state is a low wake-up latency sleeping state. In this state, no system context is lost (CPU or chip set) and hardware maintains all system context.
S2 The S2 sleeping state is a low wake-up latency sleeping state. This state is similar to the S1 sleeping state except the CPU and system cache context is lost (the OS is responsible for maintaining the caches and CPU context). Control starts from the processor""s reset vector after the wake-up event.
S3 The S3 sleeping state is a low wake-up latency sleeping state where all system context is lost except system memory. CPU, cache, and chip set context are lost in this state. Hardware maintains memory context and restores some CPU and L2 configuration context. Control starts from the processor""s reset vector after the wake-up event.
S4 The S4 sleeping state is the lowest power, longest wake-up latency sleeping state supported by ACPI. In order to reduce power to a minimum, it is assumed that the hardware platform has powered off all devices. A copy of the platform context is written to the hard disk.
S5 The S5 state is similar to the S4 state except the OS does not save any context nor enable any devices to wake the system. The system is in the xe2x80x9csoftxe2x80x9d off state and requires a complete boot when awakened.
Typically, in the PC computing architecture, data may only be transferred between two peripheral devices by having the host operating system manage such transfer. That is, the CPU, through one of its auxiliary components, must control the data flow to and from peripheral devices.
FIG. 1 is a conventional, system-level diagram of relevant components of the PC computing architecture. In this architecture, the I/O Controller Hub (ICH) 122 manages communications to and from peripheral devices 116, 118, 134 by controlling data flow to the Memory Controller Hub (MCH) 106. The bus between the ICH 122 and MCH 106 is known as the Hub Link bus 112. The MCH 106 may store data received from the ICH 122 in memory (RAM) 110 and the CPU 102 may access such data via the MCH 106.
The ICH 122 communicates with various peripheral devices and I/O components via standard buses or interfaces. Typically, the ICH 122 acts as the xe2x80x9cmasterxe2x80x9d, controlling the communication, and the peripheral device as the xe2x80x9cslavexe2x80x9d, responding to the ICH""s 122 commands. One peripheral device is a hard disk drive (HDD) 118, which may be connected to the ICH 122 via an Integrated Drive Electronics (IDE) or Extended IDE (EIDE) interface 120. The ICH 122 may also communicate with a codec (AC ""97) 116 through the AC ""97 Link 132. Other peripheral devices may also be interfaced with the ICH 122 through such interfaces as a Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), RS-232 serial port, or parallel port.
Regardless of the interface or peripheral device, the ICH 122 routes data, indicated by the dashed bidirectional lines, between said interface or device and the MCH 106 as indicated in FIG. 1. The host computer""s operating system (OS) acts as the Hub Link bus master when the CPU 102 is not in a sleeping state. When the CPU 102 is in sleeping states S3-S5, the Hub Link bus 112 is not usually operable. That is, while the CPU 102 is in these sleeping states, its resources are often unavailable and communications with the computer and its peripheral devices is not generally possible without awakening the CPU 102. Currently, the ICH 122 is designed with a single Hub Link interface and can handle only one default bus master. In order to comply with existing standards, it is desirable to avoid changing the ICH 122 architecture.
One increasingly common peripheral component in mobile computers is a mobile communications device compatible with the Bluetooth Specification. The Bluetooth Specification, v. 1.0B, Dec. 1, 1999, is a communications standard for wireless communications between mobile PCs, mobile phones, and other portable devices. This standard makes possible the interconnection of a wide range of computing and telecommunications devices via ad hoc, short-range radio links. Presently, most computers utilize external I/O devices to serve as Bluetooth-compliant transceivers. These devices are often connected to a computer via a Universal Serial Bus (USB) port or some other standard I/O interface. They also rely on the computers""CPU 102 to process the messages received and store them in memory 110. Therefore, these Bluetooth-compliant transceivers would not be able to operate during those times when the computers""CPU 102 is in a sleeping state. However, keeping the CPU 102 powered just to enable the connectivity of Bluetooth compliant devices is wasteful of the limited power available to mobile computers.
The Audio Codec ""97 (AC ""97) is a computer component which provides analog and digital audio processing functions. The AC ""97 Specification was announced Jun. 12, 1996 by co-developers Analog Devices, Inc., Creative Labs, Inc., Intel Corp., National Semiconductor Corp. and Yamaha Corp. An AC ""97 component is generally mounted on a host computer""s motherboard. On the PC computing architecture, shown in FIG. 1, the AC ""97 116 is a peripheral device coupled to the ICH 122. xe2x80x9cCoupledxe2x80x9d as used herein, includes electrically coupling two or more components.
The AC ""97 116 provides support functions for generating audio sounds. In some applications, the AC ""97 116 may be used by other peripheral devices to convert a data stream into an identifiable audio message.
Presently, the only way PC peripheral devices, such as the AC ""97 116, may be accessed is with assistance from the host operating system. That is, the CPU 102, through the Memory Controller Hub 106 and ICH 122, must control the data flow to and from peripheral devices. While the CPU 102 is in a sleeping state, its resources, including the AC ""97 116, are unavailable and cannot be accessed without awakening the CPU 102 from its sleeping state.
Accordingly, there is a need for a means to directly access a peripheral device while the host system or computer""s CPU is"" in a sleeping or suspended power management state without disrupting that power management state. In one particular application, it is desirable to have a Bluetooth-compliant device directly access an AC ""97 while the computer""s CPU is in certain power management states.